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document number: mc33937 rev. 8.0, 8/2012 freescale semiconductor advance information * this document contains certain information on a new product. specifications and information herein are subject to change without notice. ? freescale semiconductor, inc. , 2011-2012. all rights reserved. three phase field effect transistor pre-driver the 33937a is a field effect transistor (fet) pre-drivers designed for three phase motor control and si milar applications. the integrated circuit (ic) uses smartmos technology. the ic contains three high side fet pre-drivers and three low side fet pre-drivers. three external bootstrap capacitors provide gate charge to the high side fets. the ic interfaces to a mcu via six direct input control signals, an spi port for device setup and asynchronous reset, enable and interrupt signals. both 5.0 and 3.0 v logic level inputs are accepted and 5.0 v logic level outputs are provided. features ? fully specified from 8.0 to 40 v covers 12 and 24 v automotive systems ? extended operating range from 6.0 to 58 v covers 12 and 42 v systems ? greater than 1.0 a gate drive capability with protection ? protection against reverse charge injection from cgd and cgs of external fets ? includes a charge pump to support full fet drive at low battery voltages ? dead time is programmable via the spi port ? simultaneous output capability enabled via safe spi command figure 1. 33937a simplified application diagram three phase pre-driver ek suffix (pb-free) 98asa99334d 54-pin soicw-ep ordering information device (add r2 suffix for tape and reel) temperature range (t a ) package MC33937APEK -40 to 135 ? c 54 soicw-ep see document mc33937 rev. 6.0 for mcz33937ek specification. 33937a vpump pump vsup vpwr vls vdd px_hs px_ls phasex cs si sclk so rst int pa_hs_g pb_hs_g pc_hs_g pa_hs_s pb_hs_s pc_hs_s pa_ls_g pb_ls_g pc_ls_g px_ls_s amp_p amp_n amp_out gnd 33937 v sys mcu or dsp 3 3 3 r sen en1 vss en2
analog integrated circuit device data 2 freescale semiconductor 33937a internal block diagram internal block diagram figure 2. 33937a simplified internal block diagram vpump pump vsup vpwr vls vdd px_hs px_ls phasex cs si sclk so rst int amp_p amp_n amp_out px_ls_s main charge pump pgnd en1 en2 oc_out gnd(2) px_boot px_hs_g px_hs_s px_ls_g oc_th vls_cap trickle charge pump hold -off circuit oscillator control logic 5.0 v reg. vdd vls reg. uv detect t-lim + - + - + - 1.4 v + - vsup vsup + - over-cur. comp. i-sense amp. high side driver low side driver 3 3 3 3x desat. comp phase comp. vss
analog integrated circuit device data freescale semiconductor 3 33937a pin connections pin connections figure 3. 33937a pin connections table 1. 33937a pin definitions a functional description of each pin can be found in the functional pin description section beginning on page 20 . pin pin name pin function formal name definition 1 phasea digital output phase a totem pole output of phase a comparator. this output is low when the voltage on pa_hs_s (source of high side fet) is less than 50% of v sup 2 pgnd ground power ground power ground for charge pump 3 en1 digital input enable 1 logic signal input must be high (anded with en2) to enable any gate drive output. 4 en2 digital input enable 2 logic signal input must be high (anded with en1) to enable any gate drive output 5 rst digital input reset reset input 6, 33, 49, 50, 52, 53 n/c ? no connect do not connect these pins 7 pump power drive out pump charge pump output 8 vpump power input voltage pump charge pump supply 9 vsup analog input supply voltage supply voltage to the load. this pin is to be connected to the common drains of the external high side fets 10 phaseb digital output phase b totem pole output of phase b comparator. this output is low when the voltage on pb_hs_s (source of high side fet) is less than 50% of v sup 11 phasec digital output phase c totem pole output of phase c comparator. this output is low when the voltage on pc_hs_s (source of high side fet) is less than 50% of v sup 54 40 .35 34 33 32 31 30 29 28 39 38 37 36 47 46 45 44 43 42 41 51 50 49 48 53 52 1 15 20 21 22 23 24 25 26 27 16 17 18 19 8 9 10 11 12 13 14 4 5 6 7 2 3 phasea pgnd en1 en2 rst n/c pump vpump vsup phaseb phasec pa_hs pa_ls vdd pb_hs pb_ls int cs si sclk so pc_ls pc_hs amp_out amp_n amp_p oc_out vpwr n/c n/c vls n/c n/c pa_boot pa_hs_g pa_hs_s pa_ls_g pa_ls_s pb_boot pb_hs_g pb_hs_s pb_ls_g pb_ls_s pc_boot pc_hs_g pc_hs_s pc_ls_g pc_ls_s n/c vls_cap gnd1 gnd0 vss oc_th transparent top view
analog integrated circuit device data 4 freescale semiconductor 33937a pin connections 12 pa_hs digital input phase a high side active low input logic signal enables the high side driver for phase a 13 pa_ls digital input phase a low side active high input logic signal enables the low side driver for phase a 14 vdd analog output vdd regulator vdd regulator output capacitor connection. 15 pb_hs digital input phase b high side active low input logic signal enables the high side driver for phase b 16 pb_ls digital input phase b low side active high input logic signal enables the low side driver for phase b 17 int digital output interrupt interrupt pin output 18 cs digital input chip select chip select input. it frames spi commands and enables spi port 19 si digital input serial in input data for spi port. clocked on the falling edge of sclk, msb first 20 sclk digital input serial clock clock for spi port and typically is 3.0 mhz 21 so digital output serial out output data for spi port. tri-state until cs becomes low 22 pc_ls digital input phase c low side active high input logic signal enables the low side driver for phase c 23 pc_hs digital input phase c high side active low input logic signal enables the high side driver for phase c 24 amp_out analog output amplifier output output of the current-sensing amplifier 25 amp_n analog input amplifier invert inverting input of the current-sensing amplifier 26 amp_p analog input amplifier non-invert non-inverting input of the current-sensing amplifier 27 oc_out digital output over-current out totem pole digital output of the over-current comparator 28 oc_th analog input over-current threshold threshold of the over-current detector 29 vss ground voltage source supply ground reference for logic interface and power supplies 30, 31 gnd ground ground substrate and esd reference, connect to vss 32 vls_cap analog output vls regulator output capacitor vls regulator connection for additional output capacitor, providing low- impedance supply source for low side gate drive 34 pc_ls_s power input phase c low side source source connection for phase c low side fet 35 pc_ls_g power output phase c low side gate drive gate drive output for phase c low side 36 pc_hs_s power input phase c high side source source connection for phase c high side fet 37 pc_hs_g power output phase c high side gate drive gate drive for output phase c high side fet 38 pc_boot analog input phase c bootstrap bootstrap capacitor for phase c 39 pb_ls_s power input phase b low side source source connection for phase b low side fet 40 pb_ls_g power output phase b low side gate drive gate drive for output phase b low side 41 pb_hs_s power input phase b high side source source connection for phase b high side fet 42 pb_hs_g power output phase b high side gate drive gate drive for output phase b high side 43 pb_boot analog input phase b bootstrap bootstrap capacitor for phase b 44 pa_ls_s power input phase a low side source source connection for phase a low side fet table 1. 33937a pin definitions (continued) a functional description of each pin can be found in the functional pin description section beginning on page 20 . pin pin name pin function formal name definition
analog integrated circuit device data freescale semiconductor 5 33937a pin connections 45 pa_ls_g power output phase a low side gate drive gate drive for output phase a low side 46 pa_hs_s power input phase a high side source source connection for phase a high side fet 47 pa_hs_g power output phase a high side gate drive gate drive for output phase a high side 48 pa_boot analog input phase a bootstrap bootstrap capacitor for phase a 51 vls analog output vls regulator vls regulator output. power supply for the gate drives 54 vpwr power input voltage power power supply input for gate drives ep ground exposed pad device will perform as specifi ed with the exposed pad un-terminated (floating) however, it is recommended that the exposed pad be terminated to pin 29 (vss) and system ground table 1. 33937a pin definitions (continued) a functional description of each pin can be found in the functional pin description section beginning on page 20 . pin pin name pin function formal name definition
analog integrated circuit device data 6 freescale semiconductor 33937a electrical characteristics maximum ratings electrical characteristics maximum ratings table 2. maximum ratings all voltages are with respect to v ss unless otherwise noted. exceeding these rati ngs may cause a malfunction or permanent damage to the device. ratings symbol value unit electrical ratings vsup supply voltage normal operation (steady-state) transient survival (1) v sup 58 -1.5 to 80 v vpwr supply voltage normal operation (steady-state) transient survival (1) v pwr 58 -1.5 to 80 v charge pump (pump, vpump) v pump -0.3 to 40 v vls regulator outputs (vls , vls_cap) v ls -0.3 to 18 v logic supply voltage v dd -0.3 to 7.0 v logic output (int, so, phasea, phaseb, phasec, oc_out) (2) v out -0.3 to 7.0 v logic input pin voltage (en1, en2, px_hs , px_ls, si, sclk, cs , rst ) 10 ma v in -0.3 to 7.0 v amplifier input voltage (both inputs-gnd), (amp_p - gnd) or (amp_n - gnd) 6.0 ma source or sink v in_a -7.0 to 7.0 v over-current comparator threshold 10 ma v oc -0.3 to 7.0 v driver output voltage (3) high side bootstrap (pa_bo ot, pb_boot, pc_boot) high side (pa_hs_g, pb_hs_g, pc_hs_g) low side (pa_ls_g, pb_ls_g, pc_ls_g) v boot v hs_g v ls_g 75 75 16 v driver voltage transient survival (4) high side (pa_hs_g, pb_hs_g, pc_hs_g, pa_hs_s, pb_hs_s, pc_hs_s) low side (pa_ls_g, pb_ls_g, pc_ls _g, pa_ls_s, pb_ls_s, pc_ls_s) v hs_g v hs_s v ls_g v ls_s -7.0 to 75.0 -7.0 to 75.0 -7.0 to 18.0 -7.0 to 7.0 v notes 1. the device will withstand load dump transient as defined by iso7637 with peak voltage of 80 v. 2. short-circuit proof, the device will not be damaged or induce unexpected behavior due to shorts to external sources within th is range. 3. this voltage should not be applied without also taking voltage at hs_s and voltage at px_ls_s into account. 4. actual operational limitations may di ffer from survivability limits. the v ls - v ls_s differential and the v boot - v hs_s differential must be greater than 3.0 v to insure the output gate drive will maintain a commanded off condition on the output.
analog integrated circuit device data freescale semiconductor 7 33937a electrical characteristics maximum ratings esd voltage (5) human body model - hbm (all pins except for the pins listed below) pins: pa_boot, pa_hs_s, pa_hs_g, pb_boot, pb_hs_s, pb_hs_g, pc_boot, pc_hs_s, pc_hs_g, vpwr charge device model - cdm corner pins all other pins v esd 2000 1000 750 300 v thermal ratings storage temperature t stg -55 to +150 c operating junction temperature t j -40 to +150 c thermal resistance (6) junction-to-case r ? jc 3.0 c/w soldering temperature (7) t solder note 8 c notes 5. esd testing is performed in accordance with the human body model (hbm) (c zap = 100 pf, r zap = 1500 w) and the charge device model (cdm), robotic (c zap = 4.0 pf). 6. case is considered ep - pin 55 under the body of the device. the actual power dissipation of the device is dependent on the o perating mode, the heat transfer characteristics of the board and layout and the operating voltage. see figure 24 and figure 25 for examples of power dissipation profiles of two common configurations. operation above the maximu m operating junction temperature will result in a reduction in reliability leading to malf unction or permanent damage to the device. 7. pin soldering temperature limit is for 10 seconds maximum dura tion. not designed for immersion so ldering. exceeding these lim its may cause malfunction or permanent damage to the device. 8. freescale?s package reflow capability meets pb-free requirements for jedec standard j-std-020c. for peak package reflow temperature and moisture sensitivity levels (msl), go to www.free scale.com, search by part number [e.g. remove prefixes/suffixe s and enter the core id to view all orderable parts. (i.e. mc33xxxd enter 33xxx), and review parametrics. table 2. maximum ratings (continued) all voltages are with respect to v ss unless otherwise noted. exceeding these rati ngs may cause a malfunction or permanent damage to the device. ratings symbol value unit
analog integrated circuit device data 8 freescale semiconductor 33937a electrical characteristics static electrical characteristics static electrical characteristics table 3. static electr ical characteristics characteristics noted under conditions 8.0 v ? v pwr = v sup ? 40 v ?? -40 ? c ? t a ? 135 ? c, unless otherwise noted. typical values noted reflect the approximate parameter means at t a = 25 c under nominal conditions, unless otherwise noted. characteristic symbol min typ max unit power inputs vpwr supply voltage startup threshold (9) v pwr_st ? 6.0 8.0 v vsup supply current, v pwr = v sup = 40 v rst and enable = 5.0 v no output loads on gate drive pins, no pwm no output loads on gate drive pins, 20 khz, 50% duty cycle i sup ? ? 1.0 ? ? 10 ma vpwr supply current, v pwr = v sup = 40 v rst and enable = 5.0 v no output loads on gate drive pins, no pwm, outputs initialized output loads = 620 nc per fet, 20 khz pwm (10) i pwr_on ? ? 11 ? 20 95 ma sleep state supply current, rst = 0 v v sup = 40 v v pwr = 40 v i sup i pwr ? ? 14 56 30 100 a sleep state output gate voltage ig < 100 a v gatess ? ? 1.3 v trickle charge pump (bootstrap voltage) (14) v sup = 14 v v boot 22 28 32 v bootstrap diode forward voltage at 10 ma v f ? ? 1.2 v vdd internal regulator v dd output voltage, v pwr = 8 to 40 v, c = 0.47 f (11) external load i dd_ext = 0 to 1.0 ma v dd 4.5 ? 5.5 v internal v dd supply current, v dd = 5.5 v, no external load i dd ? ? 12 ma vls regulator peak output current, v pwr = 16 v, v ls = 10 v i peak 350 600 800 ma linear regulator output voltage, i vls = 0 to 60 ma,v pwr > v ls + 2.0 v (12) v ls 13.5 15 17 v vls disable threshold (13) v thvls 7.5 8.0 8.5 v notes 9. operation with the charge pump is recommended when minimum system voltage could be less than 14 v. v pwr must exceed this threshold in order for the charge pump and v dd regulator to startup and drive v pwr to > 8.0 v. once v pwr exceeds 8.0 v, the circuits will continue to operate even if system voltage drops below 6.0 v. 10. this parameter is guaranteed by design. it is not production tested. 11. minimum external capacitor for stable v dd operation is 0.47 f. 12. recommended external capacitor for the v ls regulator is 2.2 f low esr at each pin vls and vls_cap. 13. when v ls is less than this value, the outputs are disabled and holdof f circuits are active. recovery requires initialization when v ls rises above this threshold again. a filter delay of approximately 700 ns on the comparat or output eliminates responses to spurio us transients on v ls . 14. see figure 11 for typical capability to maintain gate voltage with a 5.0 a load.
analog integrated circuit device data freescale semiconductor 9 33937a electrical characteristics static electrical characteristics charge pump charge pump high side switch on resistance low side switch on resistance regulation threshold difference (15) , (17) r ds(on)_hs r ds(on)_ls v threg ? ? 250 6.0 5.0 500 10 9.4 900 ? ? mv charge pump output voltage (16) , (17) i out = 40 ma, 6.0 v < v sys < 8.0 v i out = 40 ma, v sys > = 8.0 v v cp 8.5 12 9.5 ? ? ? v gate drive high side driver on resistance (sourcing) v pwr = v sup = 16 v, -40 ? c ? t a ? 25 ? c v pwr = v sup = 16 v, 25 ? c ?? t a ? 135 ? c r ds(on)_h_src ? ? ? ? 6.0 8.5 ? high side driver on resistance (sinking) v pwr = v sup = 16 v r ds(on)_h_sink ? ? 3.0 ? high side current injection allowed without malfunction (17) , (18) i hs_inj ? ? 0.5 a low side driver on resistance (sourcing) v pwr = v sup = 16 v, -40 ? c ? t a ? 25 ? c v pwr = v sup = 16 v, 25 ? c ?? t a ? 135 ? c r ds(on)_l_src ? ? ? ? 6.0 8.5 ? low side driver on-resistance (sinking) v pwr = v sup = 16 v r ds(on)_l_sink ? ? 3.0 ? low side current injection allowed without malfunction (17) , (18) i ls_inj ? ? 0.5 ? gate source voltage, v pwr = v sup = 40 v high side, i gate = 0 (19) low side, i gate = 0 v gs_h v gs_l 13 13 14.8 15.4 16.5 17 v reverse high side gate holding voltage (20) gate output holding current = 2.0 a gate output holding current = 5.0 a, v sup <26 v gate output holding current = 5.0 a, v sup <40 v v hs_g_hold ? ? ? 10 10 ? 15 15 15 v notes 15. when vls is this amount below the normal vls linear regulation threshold, the charge pump is enabled. 16. v sys is the system voltage on the input to the charge pump. recommended external components: 1.0 f mlc, mur 120 diode. 17. this parameter is a design char acteristic, not production tested. 18. current injection only occurs during output switch transitions . the ic is immune to specified injected currents for a durati on of approximately 1.0 s after an output switch transition. 1.0 s is sufficient for all intende d applications of this ic. 19. if a slightly higher gate voltage is required, larger bootst rap capacitors are required. at high duty cycles, the bootstrap voltage may not recover completely, leading to a higher outpu t on-resistance. this effect can be mini mized by using low esr capacitors for the bootstrap and the vls capacitors. 20. high side gate holding voltage is the voltage between the gate and source of the high side fet when held in an on condition. the trickle charge pump supplies bias and holding current for the high side fet gate driver and output to maintain voltages after b ootstrap events. see figure 11 for typical 100% high side gate voltage with a 5.0 a l oad. this parameter is a design characteristic, not production tested. table 3. static electrical characteristics (continued) characteristics noted under conditions 8.0 v ? v pwr = v sup ? 40 v ?? -40 ? c ? t a ? 135 ? c, unless otherwise noted. typical values noted reflect the approximate parameter means at t a = 25 c under nominal conditions, unless otherwise noted. characteristic symbol min typ max unit
analog integrated circuit device data 10 freescale semiconductor 33937a electrical characteristics static electrical characteristics over-current comparator common mode input range (22) v cm 2.0 ? v dd -0.02 v input offset voltage v os_oc -50 ? 50 mv over-current comparator threshold hysteresis (21) v oc_hyst 50 300 mv output voltage high level at i oh = -500 a low level at i ol = 500 a v oh v ol 0.85 v dd ? ? ? v dd 0.5 v hold off circuit hold off current (at each gate pin) 3.0 v < v sup < 40 v, v gate = 1.0 v (23) i hold 10 ? 300 a phase comparator high level input voltage threshold v ih_th 0.5 v sup ? 0.65 v sup v low level input voltage threshold v il_th 0.3 v sup ? 0.45 v sup v high level output voltage at i oh = -500 a v oh 0.85 v dd ? v dd v low level output voltage at i ol = 500 a v ol ? ? 0.5 v high side source input resistance (21) , (26) r in ? 40 ? k ? desaturation detector desaturation detector threshold (24) v des_th 1.2 1.4 1.6 v current sense amplifier recommended external series resistor (see figure 9 ) r s ? 1.0 ? k ? recommended external feedback resistor (see figure 9 ) (27) limited by the output voltage dynamic range r fb 5.0 ? 15 k ? maximum input differential voltage (see figure 9 ) v id = v amp_p - v amp_n v id -800 ? +800 mv input common mode range (21) , (25) v c m -0.5 ? 3.0 v input offset voltage r s = 1.0 k ? , v cm = 0.0 v v os -15 ? +15 mv input offset voltage drift (21) ? v os / ? t ? -10 ? v/c input bias current v cm = 2.0 v i b -200 ? +200 na notes 21. this parameter is a design char acteristic, not production tested. 22. as long as one input is in the common mode range there is no phase inversion on the output. 23. the hold off circuit is designed to oper ate over the full operating range of v sup . the specification indicate s the conditions used in production test. hold off is activated at v por or v thvls. 24. desaturation is measured as the voltage drop below v sup , thus the threshold is compared to the drain-source voltage of the external high side fet. see figure 5 . 25. as long as one input is within v cm the output is guaranteed to have the correct phas e. exceeding the common mode rails on one input will not cause a phase inversion on the output. 26. input resistance is impedance from the hi gh side source and is referenced to v ss . approximate tolerance is ? 20 ?? 27. the current sense amplifier is unity gain stabl e with a phase margin of approximately 45. see figure 10 . table 3. static electrical characteristics (continued) characteristics noted under conditions 8.0 v ? v pwr = v sup ? 40 v ?? -40 ? c ? t a ? 135 ? c, unless otherwise noted. typical values noted reflect the approximate parameter means at t a = 25 c under nominal conditions, unless otherwise noted. characteristic symbol min typ max unit
analog integrated circuit device data freescale semiconductor 11 33937a electrical characteristics static electrical characteristics current sense amplifier (continued) input offset current i os = i amp_p - i amp_n i os -80 ? +80 na input offset current drift (28) ? i os / ? t ? 40 ? pa/c output voltage high level with r load = 10 k ? to v ss low level with r load = 10 k ? to v dd v oh v ol v dd -0.2 ? ? ? v dd 0.2 v differential input resistance r i 1.0 ? ? m ? output short-circuit current i sc 5.0 ? ? ma common mode input capacitance at 10 khz (28) , (29) c i ? ? 10 pf common mode rejection ratio at dc cmrr = 20*log ((v out_diff /v in _ diff ) * (v in _ cm /v out _ cm )) cmrr 60 80 ? db large signal open loop voltage gain (dc) (28) , (29) a ol ?78?db nonlinearity (28) , (29) rl = 1.0 k ? , c l = 500 pf, 0.3 < v o < 4.8 v, gain = 5.0 to 15 nl -1.0 ? +1.0 % notes 28. this parameter is a design char acteristic, not production tested. 29. without considering any offsets such as input offset voltage, internal mismatch and assuming no tolerance error in external resistors. table 3. static electrical characteristics (continued) characteristics noted under conditions 8.0 v ? v pwr = v sup ? 40 v ?? -40 ? c ? t a ? 135 ? c, unless otherwise noted. typical values noted reflect the approximate parameter means at t a = 25 c under nominal conditions, unless otherwise noted. characteristic symbol min typ max unit
analog integrated circuit device data 12 freescale semiconductor 33937a electrical characteristics static electrical characteristics supervisory and control circuits logic inputs (px_ls, px_hs , en1, en2) (31) high level input voltage threshold low level input voltage threshold v ih v il 2.1 ? ? ? ? 0.9 v logic inputs (si, sclk, cs ) (30) , (31) high level input voltage threshold low level input voltage threshold v ih v il 2.1 ? ? ? ? 0.9 v input logic threshold hysteresis (30) inputs px_ls, si, sclk, cs , px_hs , en1, en2 v ihys 100 250 450 mv input pull-down current, (px_ls, si, sclk, en1, en2) 0.3 v dd ? v in ? ? v dd ? i inpd 8.0 ? 18 a input pull-up current, (cs , px_hs ) (32) 0 ? v in ?? 0.7 ? v dd i inpu 10 ? 25 a input capacitance (30) 0.0 v ? v in ?? 5.5 v c in ? 15 ? pf rst threshold (33) v th_rst 1.0 ? 2.1 v rst pull-down resistance 0.3 v dd ? v in ? ? v dd r rst 40 60 85 k ? power-off r st threshold, (v dd falling) v por 3.4 4.0 4.5 v so high level output voltage i oh = 1.0 ma v soh 0.9 v dd ? ? v so low level output voltage i ol = 1.0 ma v sol ? ? 0.1 v dd v so tri-state leakage current cs = 0.7 v dd , 0.3 v dd ? v so ? 0.7 v dd i so_leak_t -1.0 ? 1.0 a so tri-state capacitance (30) , (34) 0.0 v ? v in ?? 5.5 v c so_t ? 15 ? pf int high level output voltage i oh = -500 a v oh 0.85 v dd ? v dd v int low level output voltage i ol = 500 a v ol ? ? 0.5 v thermal warning thermal warning temperature (30) , (35) t warn 150 170 185 c thermal hysteresis (30) t hyst 8.0 10 12 c notes 30. this parameter is guaranteed by design, not production tested. 31. logic threshold voltages derived re lative to a 3.3 v 10% system. 32. pull-up circuits will not allow back biasing of v dd. 33. there are two elements in the rst circuit: 1) one generally lower th reshold enables the internal regulator; 2) the second removes the reset from the internal logic. 34. this parameter applies to the off state (tri-stated) condi tion of so is guaranteed by desig n but is not production tested. 35. the thermal warning circuit does not forc e ic shutdown above this temperature. it is possible to set a bit in the mask regis ter to generate an interrupt when overtemperature is detected, and the stat us bit will always indicate if any of the three individual thermal warning circuits in the ic sense a fault. table 3. static electrical characteristics (continued) characteristics noted under conditions 8.0 v ? v pwr = v sup ? 40 v ?? -40 ? c ? t a ? 135 ? c, unless otherwise noted. typical values noted reflect the approximate parameter means at t a = 25 c under nominal conditions, unless otherwise noted. characteristic symbol min typ max unit
analog integrated circuit device data freescale semiconductor 13 33937a electrical characteristics dynamic electrical characteristics dynamic electrical characteristics table 4. dynamic electr ical characteristics characteristics noted under conditions 8.0 v ? v pwr = v sup ? 40 v, -40 ? c ? t a ? 135 ? c, unless otherw ise noted. typical values noted reflect the approximate parameter means at t a = 25 c under nominal conditions, unless otherwise noted. characteristic symbol min typ max unit internal regulators v dd power-up time (until int high) 8.0 v ?? v pwr (36) , (43) t pu_vdd ? ? 2.0 ms vls power-up time 16 v ?? v pwr (37) , (43) t pu_vls ? ? 2.0 ms charge pump charge pump oscillator frequency f osc 90 125 190 khz charge pump slew rate (38) sr cp ? 100 ? v/s gate drive high side turn on time (39) transition time from 1.0 to 10 v, load: c = 500 pf, rg = 0, ( figure 7 ) t onh ? 20 35 ns high side turn on delay (40) delay from command to 1.0 v, ( figure 7 ) t d_onh 130 265 386 ns high side turn off time (39) transition time from 10 to 1.0 v, load: c = 500 pf, rg = 0, ( figure 8 ) t offh ? 20 35 ns high side turn off delay (40) delay from command to 10 v, ( figure 8 ) t d_offh 130 265 386 ns low side turn on time (39) transition time from 1.0 to 10 v, load: c = 500 pf, rg = 0, ( figure 7 ) t onl ? 20 35 ns low side turn on delay (40) delay from command to 1.0 v, ( figure 7 ) t d_onl 130 265 386 ns low side turn off time (39) transition time from 10 to 1.0 v, load: c = 500 pf, rg = 0, ( figure 8 ) t offl ? 20 35 ns low side turn off delay (40) delay from command to 10 v, ( figure 8 ) t d_offl 130 265 386 ns same phase command delay match (41) t d_diff -20 0.0 +20 ns thermal filter duration (42) t dur 8.0 ? 30 s notes 36. the power-up time of the ic depends in part on the time requi red for this regulator to char ge up the external filter capacit or on v dd . 37. the power-up time of the ic depends in part on the time requi red for this regulator to charge up the external filter capacit ors on vls and vls_cap. this delay includes the expected time for v dd to rise. 38. the charge pump operating at 12 v v sys , 1.0 ? f pump capacitor, mur120 diodes and 47 f filter capacitor. 39. this parameter is guaranteed by c haracterization, not production tested. 40. these delays include all logic delays except deadtime. all inter nal logic is synchronous with t he internal clock. the total delay includes one clock period for state machine decision block, an additional cl ock period for fullon mux logi c, input synchronization time and output driver propagation delay. subtract one clock period for op eration in fullon mode which bypasses the state machine decisi on block. synchronization time accounts for up to one clock period of variation. see figure 6 . 41. the maximum separation or overlap of the high and low si de gate drives, due to propagation delays when commanding one on and the other off simultaneously, is guaranteed by design. 42. the output of the overtemperature comparator goes through a digital filter before generating a warning or interrupt. 43. this specification is based on capacitance of 0.47 f on vdd, 2.2 f on vls and 2.2 f on vls_cap.
analog integrated circuit device data 14 freescale semiconductor 33937a electrical characteristics dynamic electrical characteristics gate drive (continued) duty cycle (44) , (45) t dc 0.0 ? 96 % 100% duty cycle duration (44) , (45) t dc ? ? unlimited s maximum programmable deadtime (46) t max 10.2 15 19.6 s over-current comparator over-current protection filter time t oc 0.9 ? 3.5 s rise time (oc_out) 10% - 90% c l = 100 pf t roc 10 ? 240 ns fall time (oc_out) 90% - 10% c l = 100 pf t foc 10 ? 200 ns desaturation detector and phase comparator phase comparator propagation delay time to 50% of v dd ; c l ?? 100 pf rising edge delay falling edge delay t r t f ? ? ? ? 200 350 ns phase comparator match (prop delay mismatch of three phases) c l = 100 pf (44) t match ? ? 100 ns desaturation and phase error blanking time (47) t blank 4.7 7.1 9.1 s desaturation filter time (filter time is digital) (44) fault must be present for this time to trigger t filt 640 937 1231 ns current sense amplifier output settle time to 99% (44) , (48) rl = 1.0 k ? , c l = 500 pf, 0.3 v < v o < 4.8 v, gain = 5 to 15 t settle ? 1.0 2.0 s notes 44. this parameter is guaranteed by design, not production tested. 45. as duty cycle approaches the limit of 100% or 0% there is a maximum and minimum which is not achievable due to deadtime, propagation delays, switching times and charge time of the bootst rap capacitor (for the high side fet). 0% is available by defi nition (fet always off) and unlimited on (100%) is possible as long as gate charge maintenanc e current is within the trickle charge pu mp capacity. 46. a minimum deadtime of 0.0 can be set via an spi command. when deadtime is set via a deadtime command, a minimum of 1 clock cycle duration and a maximum of 255 clock cycl es is set using the internal time base clock as a reference. commands exceeding t his value limits at this value. 47. blanking time, t blank , is applied to all phases si multaneously when switching on any output fe t. this precludes false errors due to system noise during the switching event. 48. without considering any offsets such as input offset voltage, internal mismatch and assuming no tolerance error in external resistors. table 4. dynamic electrical characteristics (continued) characteristics noted under conditions 8.0 v ? v pwr = v sup ? 40 v, -40 ? c ? t a ? 135 ? c, unless otherw ise noted. typical values noted reflect the approximate parameter means at t a = 25 c under nominal conditions, unless otherwise noted. characteristic symbol min typ max unit
analog integrated circuit device data freescale semiconductor 15 33937a electrical characteristics dynamic electrical characteristics current sense amplifier (continued) output rise time to 90% (50) rl = 1.0 k ? , c l = 500 pf, 0.3 v < v o < 4.8 v, gain = 5.0 to 15 t is_rise ? ? 1.0 s output fall time to 10% (50) rl = 1.0 k ??? c l = 500 pf, 0.3 v < v o < 4.8 v, gain = 5.0 to 15 t is_fall ? ? 1.0 s slew rate at gain = 5.0 (49) rl = 1.0 k ? , c l = 20 pf sr (5) 5.0 ? ? v/s phase margin at gain = 5.0 (49) f m ?30? unity gain bandwidth (49) rl = 1.0 k ? , c l = 100 pf g bw ?20? mhz bandwidth at gain = 15 (49) r l = 1.0 k ? , c l = 50 pf bw g 2.0 ? ? mhz common mode rejection (cmr) (49) with v in v in_cm = 400 mv*sin(2* ? *freq*t) v in _ dif = 0.0 v, rs = 1.0 k ? r fb = 15 k ? , v refin = 0.0 v cmr = 20*log(v out /v in _ cm ) freq = 100 khz freq = 1.0 mhz freq = 10 mhz cmr 50 40 30 ? ? ? ? ? ? db supervisory and control circuits en1 and en2 propagation delay t prop ? ? 280 ns int rise time cl = 100 pf t rint 10 ? 250 ns int fall time cl = 100 pf t fint 10 ? 200 ns int propagation time t propint ? ? 250 ns rst transition time (rise and fall) (49) , (51) t trrst ? ? 1.25 s notes 49. this parameter is guaranteed by design, not production tested. 50. rise and fall times are measured from the transition of a st ep function on the input to 90% of the change in output voltage. 51. t trrst is given as a design guideline. the bounds for this specification are vpwr ? 58 v, total capacitance on vls > 1.0 f. table 4. dynamic electrical characteristics (continued) characteristics noted under conditions 8.0 v ? v pwr = v sup ? 40 v, -40 ? c ? t a ? 135 ? c, unless otherw ise noted. typical values noted reflect the approximate parameter means at t a = 25 c under nominal conditions, unless otherwise noted. characteristic symbol min typ max unit
analog integrated circuit device data 16 freescale semiconductor 33937a electrical characteristics timing diagrams timing diagrams figure 4. spi interface timing spi interface timing maximum frequency of spi operation f op ? 4.0 mhz internal time base f tb 13 17 25 mhz internal time base drift from value at 25 ? c (52) tc tb -5.0 ? 5.0 % falling edge of cs to rising edge of sclk (required setup time) (52) t lead 100 ? ? ns falling edge of sclk to rising edge of cs (required setup time) (52) t lag 100 ? ? ns si to falling edge of sclk (required setup time) (52) t sisu 25 ? ? ns falling edge of sclk to si (required setup time) (52) t sihold 25 ? ? ns si, cs , sclk signal rise time (52) , (53) t rsi ? 5.0 ? ns si, cs , sclk signal fall time (52) , (53) t fsi ? 5.0 ? ns time from falling edge of cs to so low-impedance (52) , (54) t soen ? 55 100 ns time from rising edge of cs to so high-impedance (52) , (55) t sodis ? 100 125 ns time from rising edge of sclk to so data valid (52) , (56) t valid ? 80 125 ns time from rising edge of cs to falling edge of the next cs (52) t dt 200 ? ? ns notes 52. this parameter is guaranteed by design, not production tested. 53. rise and fall time of incoming si, cs , and sclk signals suggested for design considerat ion to prevent the oc currence of double pulsing. 54. time required for valid output status data to be available on so pin. 55. time required for output states data to be terminated at so pin. 56. time required to obtain valid data out from so following the rise of sclk with 200 pf load. table 4. dynamic electrical characteristics (continued) characteristics noted under conditions 8.0 v ? v pwr = v sup ? 40 v, -40 ? c ? t a ? 135 ? c, unless otherw ise noted. typical values noted reflect the approximate parameter means at t a = 25 c under nominal conditions, unless otherwise noted. characteristic symbol min typ max unit t do (dis) 0.7 v dd 0. 2 v dd 0.2 v dd 0.7 v dd 0.2 v dd t lead t di(su) t di(ho ld) t valid t lag cs sclk si so msb in msb out lsb out 0.7 v dd 0.2 v dd t do(en) t sodis t soen t sisu t sihold t lag
analog integrated circuit device data freescale semiconductor 17 33937a electrical characteristics timing diagrams figure 5. desaturation bl anking and filtering detail figure 6. deadtime control delays figure 7. driver turn-on time and turn-on delay from delay timer p x _hs p x _ls desaturation fault p x _ls p x _hs en1 en2 rst state deadtime control 1 st pulse machine p x _hs_g p x _hs_s p x _ls_g dq clk d q clk dq clk dq clk dq clk dq clk b out a mux b out a mux 50 % px_hs _g px_hs 10v 1.0v t d_onh t onh 50% px_ls_g px_ls 10v 1.0v t d_onl t onl
analog integrated circuit device data 18 freescale semiconductor 33937a electrical characteristics timing diagrams figure 8. driver turn-off time and turn-off delay figure 9. current amplifier and input waveform (v in voltage across r sense ) 50% 10v 1.0v t d_offl t offl px_ls_g px_ ls px_hs_g px_hs 50% 10v 1.0v t d_offh t offh v in - ref r sense amp_out amp_p amp_n oc_th v id r f bn r fb p r s r s + + - to protection circuits 0v 0v -400mv to + 400mv -400mv to + 400mv 0.5s - 50s 0.5s - 50s 0s - 0.5s
analog integrated circuit device data freescale semiconductor 19 33937a electrical characteristics timing diagrams figure 10. typical amplifier open-loop gain and phase vs. frequency figure 11. typical high side 100% on gate voltage with 5.0 a gate load gain (db) phase (degrees) gain phase 16 typicalhighside100%ongatevoltagewith5 agateload v sup =40v 14 v sup =24v sup 10 12 v sup =9v v sup =14v 8 v cboot v hs_s (v) 4 6 2 0 50 30 10 10 30 50 70 90 110 130 150 temperature(c)
analog integrated circuit device data 20 freescale semiconductor 33937a functional descriptions introduction functional descriptions introduction the 33937a provides an interface between an mcu and the large fets used to drive three phase loads. a typical load fet may have an on resistance of 4.0 m ? or less and could require a gate charge of over 400 nc to fully turn on. the ic can operate in automotive 12 to 42 v environments. because there are so many methods of controlling three phase systems, the ic enforces few constraints on driving the fets. it does provide deadtime (cross-over) blanking and logic, both of which can be overridden, ensuring both fets in a phase are not simultaneously enabled. an spi port is used to configure the ic modes. functional pin description phase a (phasea) this pin is the totem pole output of the phase a comparator. this output is low when the voltage on phase a high side source (source of the high side load fet) is less than 50 percent of vsup. power ground (pgnd) this pin is power ground for the charge pump. it should be connected to vss, however routing to a single point ground on the pcb may help to isolate charge pump noise. enable 1 and enable 2 (en1, en2) both of these logic signal inputs must be high to enable any gate drive output. when either or both are low, the internal logic (spi port, etc.) still functions normally, but all gate drives are forced off (external power fet gates pulled low). the signal is asynchronous. when en1 and en2 return high to enable the outputs, each ls driver must be pulse d on before the corresponding hs driver can be commanded on. this ensures that the bootstrap capacitors are charged. see initialization requirements on page 37 . reset (rst ) when the reset pin is low the integrated circuit (ic) is in a low power state. in this mode all outputs are disabled, internal bias circuits are turned off, and a small pull-down current is applied to the output gate drives. the internal logic will be reset within 77 ns of reset going low. when rst is low, the ic will consume minimal current. charge pump out (pump) this pin is the switching node of the charge pump circuit. the output of the internal charge pump support circuit. when the charge pump is used, it is connected to the external pumping capacitor. this pin may be left floating if the charge pump is not required. charge pump input (vpump) this pin is the input supply for the charge pump circuit. when the charge pump is required, this pin should be connected to a polarity protected supply. this input should never be connected to a supply greater than 40 v. if the charge pump is not required this pin may be left floating. vsup input (vsup) the supply voltage pin should be connected to the common connection of the high side fets. it is the reference bias for the phase comparators and desaturation comparator. it is also used to provide power to the internal steady state trickle charge pump and to energize the hold off circuit. phase b (phaseb) this pin is the totem pole output of the phase b comparator. this output is low when the voltage on phase b high side source (source of the high side load fet) is less than 50 percent of v sup . phase c (phasec) this pin is the totem pole output of the phase c comparator. this output is low when the voltage on phase c high side source (source of the high side load fet) is less than 50 percent of v sup . phase a high side input (pa_hs ) this input logic signal pin enables the high side driver for phase a. the signal is active low, and is pulled up by an internal current source. phase a low side input (pa_ls) this input logic signal pin enables the low side driver for phase a. the signal is active high, and is pulled down by an internal current sink. vdd voltage regulator (vdd) vdd is an internally generated 5.0 v supply. the internal regulator provides continuous power to the ic and is a supply reference for the spi port. a 0.47 f (min) decoupling capacitor must be connected to this pin.
analog integrated circuit device data freescale semiconductor 21 33937a functional descriptions introduction this regulator is intended for internal ic use and can supply only a small (1.0 ma) external load current. a power-on-reset (por) circuit monitors this pin and until the voltage rises above the threshold, the internal logic will be reset; driver outputs will be tri-stated and spi communication disabled. the vdd regulator can be disabled by asserting the rst signal low. the vdd regulator is powered from the vpwr pin. phase b high side control input (pb_hs ) this pin is the input logic signal, enabling the high side driver for phase b. the signal is active low, and is pulled up by an internal current source. phase b low side input (pb_ls) this pin is the input logic signal, enabling the low side driver for phase b. the signal is active high, and is pulled down by an internal current sink. interrupt (int) the interrupt pin is a totem pole logic output. when a fault is detected, this pin will pull high until it is cleared by executing the clear interrupt command via the spi port. the faults capable of causing an interrupt can be masked via the mask0 and mask1 spi registers to customize the response. chip select (cs ) chip select is a logic input that frames the spi commands and enables the spi port. this signal is active low, and is pulled up by an internal current source. serial in (si) the serial in pin is used to input data to the spi port. clocked on the falling edge of sclk , it is the most significant bit (msb) first. this pin is pulled down by an internal current sink. serial clock (sclk) this logic input is the clock is used for the spi port. the sclk typically runs at 3.0 mhz (up to 5.0 mhz) and is pulled down by an internal current sink. serial out (so) output data for the spi port streams from this pin. it is tri- stated until cs is low. new data appears on rising edges of sclk in preparation for latching by the falling edge of sclk on the master. phase c low side input (pc_ls) this input logic pin enables the low side driver for phase c. this pin is an active high, and is pulled down by an internal current sink. phase c high side input (pc_hs ) this input logic pin enables the high side driver for phase c. this signal is active low, and is pulled up by an internal current source. amplifier output (amp_out) this pin is the output for the current sensing amplifier. it is also the sense input to the over-current comparator. amplifier inverting input (amp_n) the inverting input to the current sensing amplifier. amplifier non-inverting input (amp_p) the non-inverting input to the current sensing amplifier. over-current comparator output (oc_out) the over-current comparator output is a totem pole logic level output. a logic high indicates an over-current condition. over-current comparator threshold (oc_th) this input sets the threshold level of the over-current comparator. voltage source supply (vss) vss is the ground reference for the logic interface and power supplies. ground (gnd0,gnd1) these two pins are connected internally to vss by a 1.0 ? resistor. they provide device substrate connections and also the primary return path for esd protection. vls regulator capacitor (vls_cap) this connection is for a capacitor which will provide a low- impedance for switching currents on the gate drive. a low esr decoupling capacitor, capable of sourcing the pulsed drive currents must be connec ted between this pin and vss. this is the same dc node as vls, but it is physically placed on the opposite end of the ic to minimize the source impedance to the gate drive circuits. phase c low side source (pc_ls_s) the phase c low side source is the pin used to return the gate currents from the low side fet. best performance is realized by connecting this node directly to the source of the low side fet for phase c. phase c low side gate (pc_ls_g) this is the gate drive for the phase c low side output fet. it provides high-current through a low-impedance to turn on and off the low side fet. a low-impedance drive ensures transient currents do not overcome an off-state driver and
analog integrated circuit device data 22 freescale semiconductor 33937a functional descriptions introduction allow pulses of current to flow in the external fet. this output has also been designed to resist the influence of negative currents. phase c high side source (pc_hs_s) the source connection for the phase c high side output fet is the reference voltage for the gate drive on the high side fet and also the low-voltage end of the bootstrap capacitor. phase c high side gate (pc_hs_g) this is the gate drive for the phase c high side output fet. this pin provides the gate bias to turn the external fet on or off. the gate voltage is limited to about 15 v above the fet source voltage. a low-impeda nce drive is used, ensuring transient currents do not overcome an off-state driver and allow pulses of current to flow in the external fets. this output has also been designed to resist the influence of negative currents. phase c bootstrap (pc_boot) this is the bootstrap capacitor connection for phase c. a capacitor connected between pc_hs_s and this pin provides the gate voltage and current to drive the external fet gate. typically, the bootstra p capacitor selection is 10 to 20 times the gate capacitance. the voltage across this capacitor is limited to about 15 v. phase b low side source (pb_ls_s) the phase b low side source is the pin used to return the gate currents from the low side fet. best performance is realized by connecting this node directly to the source of the low side fet for phase b. phase b low side gate (pc_ls_g) this is the gate drive for the phase b low side output fet. it provides high-current through a low-impedance to turn on and off the low side fet. a low-impedance drive ensures transient currents do not overcome an off-state driver and allow pulses of current to flow in the external fet. this output has also been designed to resist the influence of negative currents. phase b high side source (pb_hs_s) the source connection for the phase b high side output fet is the reference voltage for the gate drive on the high side fet and also the low-voltage end of the bootstrap capacitor. phase b high side gate (pb_hs_g) this is the gate drive for the phase b high side output fet. this pin provides the gate bias to turn the external fet on or off. the gate voltage is limited to about 15 v above the fet source voltage. a low-impedance drive is used, ensuring transient currents do not overcome an off-state driver and allow pulses of current to flow in the external fets. this output has also been designed to resist the influence of negative currents. phase b bootstrap (pb_boot) this is the bootstrap capacitor connection for phase b. a capacitor connected between pc_hs_s and this pin provides the gate voltage and current to drive the external fet gate. typically, the bootstrap capacitor selection is 10 to 20 times the gate capacitance. the voltage across this capacitor is limited to about 15 v. phase a low side source (pa_ls_s) the phase a low side source is the pin used to return the gate currents from the low side fet. best performance is realized by connecting this node directly to the source of the low side fet for phase a. phase a low side gate (pa_ls_g) this is the gate drive for the phase a low side output fet. it provides high-current through a low-impedance to turn on and off the low side fet. a low-impedance drive ensures transient currents do not overcome an off-state driver and allow pulses of current to flow in the external fet. this output has also been designed to resist the influence of negative currents. phase a high side source (pa_hs_s) the source connection for the phase a high side output fet is the reference voltage for the gate drive on the high side fet and also the low-voltage end of the bootstrap capacitor. phase a high side gate (pa_hs_g) this is the gate drive for the phase a high side output fet. this pin provides the gate bias to turn the external fet on or off. the gate voltage is limited to about 15 v above the fet source voltage. a low-impedance drive is used, ensuring transient currents do not overcome an off-state driver and allow pulses of current to flow in the external fets. this output has also been designed to resist the influence of negative currents. phase a bootstrap (pa_boot) this is the bootstrap capacitor connection for phase a. a capacitor connected between pc_hs_s and this pin provides the gate voltage and current to drive the external fet gate. typically, the bootstrap capacitor selection is 10 to 20 times the gate capacitance. the voltage across this capacitor is limited to about 15 v.
analog integrated circuit device data freescale semiconductor 23 33937a functional descriptions introduction vls regulator (vls) vls is the gate drive power supply regulated at approximately 15 v. this is an internally generated supply from vpwr. it is the source for the low side gate drive voltage, and also the high side bootstrap source. a low esr decoupling capacitor, capable of sourcing the pulsed drive currents, must be connected between this pin and vss. vpwr input (vpwr) vpwr is the power supply input for vls and vdd. current flowing into this input recharges the bootstrap capacitors as well as supplying power to the low side gate drivers and the vdd regulator. an internal regulator regulates the actual gate voltages. this pin can be connected to system battery voltage if power dissipation is not a concern. exposed pad (ep) the primary function of the exposed pad is to conduct heat out of the device. this pad may be connected electrically to the substrate of the device.the device will perform as specified with the exposed pad un-terminated (floating). however, it is recommended that the exposed pad be terminated to pin 29 (vss) and the system ground.
analog integrated circuit device data 24 freescale semiconductor 33937a functional internal block description functional internal block description figure 12. functional internal block description all functions of the ic can be described as the following five major functional blocks: ? logic inputs and interface ? bootstrap supply ? low side drivers ? high side drivers ? charge pump logic inputs and interface this section contains the spi port, control logic, and shoot- through timers. the ic logic inputs have schmitt trigger inputs with hysteresis. logic inputs are 3.0 v compatible. the logic outputs are driven from the internal supply of approximately 5.0 v. the spi registers and functionality is described completely in the logic commands and registers section of this document. spi functionality includes the following: ? programming of deadtime delay ?this delay is adjustable in approximately 50 ns steps from 0 ns to 12 s. calibration of the delay, because of internal ic variations, is performed via the spi. ? enabling of simultaneous operation of high side and low side fets ?normally, both fets would not be enabled simultaneously. however, for certain applications where the load is connected between the high side and low side fets, this could be advantageous. if this mode is enabled, the blanking time delay will be disabled. a sequence of commands may be required to enable this function to prevent inadvertent enabling. in addition, this command can only be executed once after reset to enable or disable simultaneous turn-on. ? setting of various operating modes of the ic and enabling of interrupt sources. the 33937a allows different operating modes to be set and locked by an spi command (fullon, desaturation fault, zero deadtime). spi commands can also determine how the various faults are (or are not) reported. ? read back of internal registers . the status of the 33937a status registers can be read back by the master (dsp or mcu). mc33937 - functional block diagram integrated supply sensing & protection drivers high side and low side output pre-drivers logic & control integrated supply trickle charge pump 5v regulator vls regulator main charge pump sensing & protection hold-off temperature current sense over-current de-sat phase under-voltage logic & control dead time fault register mode control phase control spi communication
analog integrated circuit device data freescale semiconductor 25 33937a functional internal block description the px_hs and px_ls logic inputs are edge sensitive. this means the leading edge on an input will cause the complementary output to immediately turn off and the selected one to turn on after the deadtime delay as illustrated in figure 13 . the deadtime delay timer always starts at the time a fet is commanded off and prevents the complementary fet from being commanded on until after the deadtime has elapsed. commands to turn on the complementary fet after the deadtime has elapsed are executed immediately without any further delay (see figure 6 and figure 13 ). figure 13. edge sensitiv e logic inputs (phase a) low side and bootstrap supply (vls) this is the portion of the ic providing current to recharge the bootstrap capacitors. it also supplies the peak currents required for the low side gate drivers. the power for the gate drive circuits is provided by vls which is supplied from the vpwr pin. this pin can be connected to system battery voltage and is capable of withstanding up to the full load dump voltage of the system. however, the ic only requires a low-voltage supply on this pin, typically 13 to 16 v. higher voltages on this pin will increase the ic power dissipation. in 12 v systems the supply voltage can fall as low as 6.0 v. this limits the gate voltage capable of being applied to the fets and reduces system perf ormance due to the higher fet on-resistance. to allow a higher gate voltage to be supplied, the ic also incorporates a charge pump. the switches and control circuitry are internal; the capacitors and diodes are external (see figure 22 ). low side drivers these three drivers turn on and off the external low side fets. the circuits provide a low-impedance drive to the gate, ensuring the fets remain off in the presence of high dv/dt transients on their drains. additionally, these output drivers isolate the other portions of the ic from currents capable of being injected into the substrate due to rapid dv/dt transients on the fet drains. low side drivers switch power from vls to the gates of the low side fets. the low side drivers are capable of providing a typical peak current of 2.0 a. this gate drive current may be limited by external resistors in order to achieve a good trade-off between the efficiency and emc (electro-magnetic compatibility) compliance of the application. the low side driver uses high side pmos for turn on and low side isolated ldmos for turn off. the circuit ensures the impedance of the driver remains low, even during periods of reduced current. current limit is blanked immediately after subsequent input state change in order to ensure device stays off during dv/dt transients. high side drivers these three drivers switch the voltage across the bootstrap capacitor to the external high side fets. the circuits provide a low-impedance drive to the gate, ensuring the fets remain off in the presence of high dv/dt transients on their sources. further, these output drivers isolate the other portions of the ic from currents capable of being injected into the substrate due to rapid dv/dt transients on the fets. the high side drivers deliver power from their bootstrap capacitor to the gate of the external high side fet, thus turning the high side fet on. the high side driver uses a level shifter, which allows the gate of the external high side fet to be turned off by switching to the high side fet source. the gate supply voltage for the high side drivers is obtained from the bootstrap supply, so, a short time is required after the application of power to the ic to charge the bootstrap capacitors. to ensure this occurrence, the internal control logic will not allow a high side switch to be turned on after entering the enable state until the corresponding low side switch is enabled at least once. caution must be exercised after a long period of inactivity of the low side switches to verify the bootstrap capacitor is not discharged. it will be charged by activating the low side switches for a brief period, or by attaching external bleed resistors from the hs_s pins to gnd. see initialization requirements on page 37 . in order to achieve a 100% duty cycle operation of the high side external fets, a fully integrated trickle charge pump provides the charge necessary to maintain the external fet gates at fully enhanced levels. the trickle charge pump has limited ability to supply external leakage paths while performing it?s primary function. the graph in figure 11 shows the typical margin for supplying external current loads. these limits are based on maintaining the voltage at cboot at least 3.0 v greater than the voltage on the hs_s for that phase. if this voltage differential becomes less than 3.0 v, the corresponding high side fet will most likely not remain fully enhanced and the high side driver may malfunction due to insufficient bias voltage between cboot and hs_s. the slew rate of the external output fet is limited by the driver output impedance, overall (external and internal) gate resistance and the load capacitance. to ensure the low side fet is not turned on by a large positive dv/dt on the drain of the low side fet, the turn-on slew rate of the high side should be limited. if the slew rate of the high side is limited pa _h s pa_ls pa_ h s_ g pa_ls_g de adt ime de lay
analog integrated circuit device data 26 freescale semiconductor 33937a functional internal block description by the gate-drain capacitance of the high side fet, then the displacement current injected into the low side gate drive output will be approximately the same value. therefore, to ensure the low side drivers can be held off, the voltage drop across the low side gate driver must be lower than the threshold voltage of the low side fet (see figure 14 ). similarly, during large negative dv/dt, the high side fet will be able to remain off if its gate drive low side switch, develops a voltage drop less than the threshold voltage of the high side fet. the gate drive low side switch discharges the gate to the source. additionally, during negative dv/dt the low side gate drive could be forced below ground. the low side fets must not inject detrimental substrate currents in this condition. the occurrence of these cases depends on the polarity of the load current during switching. figure 14. positive dv/dt transient driver fault protection the 33937a ic integrates several protection mechanisms against various faults. the first of them is the current sense amplifier with the over-current comparator. these two blocks are common for all three driver phases. current sense amplifier this amplifier is usually connected as a differential amplifier (see figure 9 ). it senses a current flowing through the external fets as a volt age across the current sense resistor r sense . since the amplifier common mode range does not extend below ground, it is necessary to use an external reference to permit measuring both positive and negative currents. the amplifier output can be monitored directly (e.g. by the microcontroller?s adc) at the amp_out pin, providing the means for closed loop control with the 33937a. the output voltage is internally compared with the over- current comparator threshold voltage (see figure 22 ). over-current comparator the amplified voltage across r sense is compared with the pre-set threshold value by the over-current comparator input. if the current sense amplifier output voltage exceeds the threshold of the over-current comparator it would change the status of its output (oc_out pin) and the fault condition would be latched (see figure 18 ). the occurrence of this fault would be signalled by the return value of the status register 0. if the proper interrupt mask has been set, this fault condition will generate an interrupt - the int pin will be asserted high. the int will be held in the high state until the fault is removed, and the appropriate bit in the status register 0 is cleared by the clint0 command. this fault reporting technique is described in detail in the logic commands and registers section. desaturation detector the desaturation detector is a comparator integrated into the output driver of each phase channel. it provides an additional means to protect ag ainst ?short-to-ground? fault condition. a short to ground is detected by an abnormally high-voltage drop in vds of the high side fet. note that if the gate-source voltage of the high side fet drops below saturation, the device will go into linear mode of conduction which can also cause a desaturation error. phase x output phase return px_ls_s px_ls_g px_hs_s low -si de driver ls control px_ls_g px_hs_g deadtime -v d v sup phase x output voltage dv/dt c gs c dg c ds r g i cdg vls 33927 + - g s d di scr ete fet package z o 33937a
analog integrated circuit device data freescale semiconductor 27 33937a functional internal block description figure 15. short to ground detection when switching from low side to high side, the high side will be commanded on after the end of the deadtime. the deadtime period starts when the low side is commanded off. if the voltage at px_hs_s is less than 1.4v below v sup after the blanking time (t blank ) a desaturation fault is initiated. an additional 1.0 ? s digital filter is applied from the initiation of the desaturation fault before it is registered, and all phase drivers are turned off (px_hs_g clamped to px_hs_s and px_ls_g clamp ed to px_ls_s). if the desaturation fault condition clears before the filter time expires, the fault is ignored and the filter timer resets. valid faults are registered in the fault status register, which can be retrieved by way of the spi. additional spi commands will mask the int flag and disable output stage shutdown, due to desaturation and phase errors. see the logic commands and registers section for details on masking int behavior and disabling the protective function. figure 16. short to supply detection phase comparator faults could also be detected as phase errors . a phase error is generated if the output signal (at px_hs_s) does not properly reflect the drive conditions. a phase error is detected by a phase comparator. the phase comparator compares the voltage at the px_hs_s node with a reference of one half the voltage at the vsup pin. a high side phase error (which will also trigger the desaturation detector) occurs when the high side fet is commanded on, and px_hs_s is still low at the end of the deadtime and blanking time duration. similarly, a ls phase error occurs when the low side fet is commanded on, and the px_hs_s is still high at the end of the deadtime and blanking time duration. the phase error flag is the triple or of phase errors from each phase. each phase error is the or of the high side and low side phase errors. this flag can generate an interrupt if the appropriate mask bit is set. the int will be held in the high state until the fault is removed, and the appropriate bit in the status register 0 is cleared by the clint1 command. this fault reporting mechanism is described in detail in the logic commands and registers section. v sup phase x output r sense phase return t- lim vls_cap px_ls_s px_ls_g px_hs_g px_hs_s px_boot phase comp. desat. comp. 3x + - vsup vsup 1.4v low -side driver hi gh -side driver hs control r r vls to current sense amplif. phase x output shorted to ground (low-side fet shorted) ls control px_ls_g px_hs_g deadtime -v d v sup phase x output voltage shorted to ground correct phase x output voltage 0.5v sup phasex cor rec t fault phase error t blank t filt desaturation error v sup phase x output r sense phase return t-lim vls_cap px_ls_s px_ls_g px_hs_g px_hs_s px_boot phase comp. desat. comp. 3x + - vsup vsup 1. 4v low -side driver hi gh -side driver hs control r r vls to current sense amplif. phase x output shorted to v sup (high-side fet shorted) ls control px_ls_g px_hs_g deadtime -v d v sup phase x output voltage shorted to v sup correct phase x output voltage 0.5v sup phasex correct fault phase error t blank
analog integrated circuit device data 28 freescale semiconductor 33937a functional internal block description vls under voltage since vls supplies both the gate driver circuits and the gate voltage, it is critical that it maintains sufficient potential to place the power stage fets in saturation. since proper operation cannot continue with insufficient levels, a low vls condition will shutdown driver operation. the vls under voltage threshold is between 7.5 v and 8.5 v. when a decreasing level reaches the threshold, both the hs and the ls output gate circuit drive the gates off for about 8us before reducing the drive to hold off levels. since low vls is a condition for turning on the hold off circuit, hold off then provides a weak pull-down on all gates. a filter timeout of about 700ns insures that noise on vls will not cause premature protective action. when vls rises above this threshold again, the ls gate immediately follows the level of the input. however, a short initialization sequence must be executed to restore operation of the hs gate. (see initialization requirements on page 37 ) since vls is no longer under voltage, the hold off circuit is turned off and the hs gate will be in a high-impedance state until the ls gate responds to an input command to turn off. hold off circuit the ic guarantees the output fets are turned off in the absence of v dd or v pwr by means of the hold off circuit. a small current source, generated from vsup, typically 100 a, is mirrored and pulls all the output gate drive pins low when v dd is less than about 3.0 v, rst is active (low), or when vls is lower than the vls_disable threshold. a minimum of 3.0 v is required on vsup to energize the hold off circuit. charge pump the charge pump circuit provides the basic switching elements required to implement a charge pump, when combined with external capacitors and diodes for enhanced low-voltage operation. when the 33937a is connected per the typical application using the charge pump (see figure 22 ), the regulation path for vls includes the charge pump and a linear regulator. the regulation set point for the linear regulator is nominally at 15.34 v. as long as vls output voltage (vls out ) is greater than the vls analog regulator threshold (vls ath ) minus v threg , the charge pump is not active. if vls out < vls ath ? v threg the charge pump turns on until vls out > vls ath ? v threg + v hyst v hyst is approximately 200 mv. vls ath will not interfere with this cycle even when there is overlap in the thresholds, due to the design of the regulator system. the maximum current the charge pump can supply is dependent on the pump capacitor value and quality, the pump frequency (nominally 130 khz), and the rdson of the pump fets. the effective charge voltage for the pump capacitor would be v sys ? 2 * v diode . the total charge transfer would then be c pump * (v sys ? 2*v diode ). multiplying by the switch frequency gives the theoretical current the pump can transfer: f pump * c pump * (v sys ? 2*v diode ). note: there is also another smaller, fully integrated charge pump (trickle charge pump - see figure 2 ), which is used to maintain the high side drivers? gate v gs in 100 percent duty cycle modes.
analog integrated circuit device data freescale semiconductor 29 33937a functional device operation operational modes functional device operation operational modes reset and enable the 33937a has three power modes of operation described in table 5 . there are three global control inputs (rst , en1, en2), which together with the status of vdd, vls and desat/phase faults contro l the behavior of the ic. the operating status of the ic can be described by the following five modes: ? sleep mode - when rst is low, the ic is in sleep mode. the current consumption of the ic is at minimum. ? standby mode - the rst input is high while one of the enable inputs is low. the ic is fully biased up and operating, all the external fets are actively turned off by both high side and low side gate drives. the ic is ready to enter the enable mode. ? initialization mode - when en1, en2 and rst all go high, the device enters the initialization mode. toggling the ls and then the hs initializes the driver and normal operation in the enable mode begins. (see initialization requirements on page 40) ? enable mode - after initialization is complete, the device goes into the enable mode and operates normally. normal operation continues in this mode as long as both enable pins and rst are high. ? fault protection mode - if a protective fault occurs (either desat/phase or vls uv) the device enters a fault protection mode. after a fault clears, the device requires initialization again before resuming normal enable mode operation. table 5. functions of rst , en1 and en2 pins rst en1, en2 mode of operation (driver condition) 0 xx sleep mode - in this mode (low quiescent current) the driver output stage is switched-off with a weak pull-down. all error and spi registers are cleared. the internal 5.0 v regulator is turned off and vdd is pulled low. all logic outputs except so are clamped to vss. 1 0x x0 standby mode - ic fully biased up and all functions are operating, the output drivers actively turn off all of the external fets (after initialization). the spi port is functional. logi c level outputs are driven with low-impedance. so is high- impedance unless cs is low. v dd , charge pump and v ls regulators are all operating. the ic is ready to move to enable mode. 1 11 initialization mode - low side drivers are enabled, spi is full y operational. ready for initialization (see initialization requirements on page 37 ). enable mode - (normal operation). drivers are enabled; output stage s follow the input command. after enable, outputs require a pulse on px_ls before corresponding hs outputs will turn on in order to charge the bootstrap capacitor. all error pin and register bits are active if detected. fault protection mode - drivers are turned off or disabled per t he fault and protection mode registers. recovery requires initialization (see initialization requirements on page 37 ). table 6. functional ratings ( t j = -40 c to 150 c and supply voltage range v sup = v pwr = 5.0 to 45 v, c = 0.47 f) characteristic value default state of input pin px_ls, en1, en2, rst , si, sclk, if left open (57) (driver output is switched off, high-impedance mode) low (<1.0 v) default state of input pin px_hs , cs if left open (57) (driver output is switched off, high-impedance mode) high (>2.0 v) notes 57. to assure a defined status for all inputs, these pins are internally biased by pull-up/down current sources.
analog integrated circuit device data 30 freescale semiconductor 33937a functional device operation operational modes figure 17. device operational flow diagram sleep mode initialization standby mode fault protection enable (normal) mode sleep rst n y stby en y n enable ls ls toggle hs toggle y ny n driver off disable driver desat/ vls uv y y n n enable hs desat vls uv en rst disabled n n n y y y y n y n holdoff active phase desat/ phase driver off
analog integrated circuit device data freescale semiconductor 31 33937a functional device operation logic commands and registers logic commands and registers command descriptions the ic contains internal registers to control the various operating parameters, modes, and interrupt characteristics. these commands are sent and status is read via 8-bit spi commands. the ic will use the last eight bits in an spi transfer, so devices can be daisy-chained. the first three bits in an spi word can be considered to be the command with the trailing five bits being the data. the spi logic will generate a framing error and ignore the spi message if the number of received bits is not eight or if it is not a multiple of eight. after rst , the first spi result returned is status register 0. fault reporting and interrupt generation different fault conditions described in the previous chapters can generate an interrupt - int pin output signal asserted high. when an interrupt occurs, the source can be read from status register 0, which is also the return word of most spi messages. faults are latched on occurrence, and the interrupt and faults are only cleared by sending the corresponding clintx command. a fault that still exists will continue to assert an interrupt. note: if there are multiple pending interrupts, the int line will not toggle when one of the faults is cleared. interrupt processing circuitry on the host must be level sensitive to correctly detect multiple simultaneous interrupt. thus, when an interrupt occurs, the host can query the ic by sending a null command; the return word contains flags indicating any faults not cleared since the clintx command was last written (rising edge of cs ) and the beginning of the current spi command (falling edge of cs ). the null command causes no changes to the state of any of the fault or mask bits. the logic clearing the fault latches occurs only when: 1. a valid command had been received(i.e. no framing error); 2. a state change did not occur during the spi message (if the bit is being returned as a 0 and a fault change occurs during the middle of the spi message, the latch will remain set). the latch is cleared on the trailing (rising) edge of the cs pulse. note, to prevent missing any faults the clintx command should not generally clear any faults without being observed; i.e. it should only clear faults returned in the prior null response. table 7. command list command name description 000x xxxx null these commands are used to read ic status. these co mmands do not change any internal ic status. returns status register 0-3, depending on sub command. 0010 xxxx mask0 sets a portion of the interrupt mask using lower four bits of command. a ?1? bit enables interrupt generation for that flag. int remains asserted if uncleared faul ts are still present. returns status register 0. 0011 xxxx mask1 sets a portion of the interrupt mask using lower four bits of command. a ?1? bit enables interrupt generation for that flag. int remains asserted if uncleared faul ts are still present. returns status register 0. 010x xxxx mode enables desat/phase error mode. enables fullon mode. locks further mode changes. returns status register 0. 0110 xxxx clint0 clears a portion of the fault latch corresponding to mask0 using lower four bits of command. a 1 bit clears the interrupt latch for that flag. int remains asserted if other unmasked faults are still present. returns status register 0. 0111 xxxx clint1 clears a portion of the fault latch corresponding to mask1 using lower four bits of command. a 1 bit clears the interrupt latch for that flag. int remains asserted if other unmasked faults are still present. returns status register 0. 100x xxxx deadtime set deadtime with calibration technique. returns status register 0.
analog integrated circuit device data 32 freescale semiconductor 33937a functional device operation logic commands and registers null commands this command is sent by sending binary 000x xxxx data. this c an be used to read ic status in the spi return word. message 000x xx00 reads status register 0. message 000x xx01 through 000x xx11 read additional internal registers. mask command this is the mask for interrupts. a bit set to ?1? enables the corresponding interrupt. because of the number of mask bits, this register is in two portions: 1. mask0 2. mask1 both are accessed with 0010 xxxx and 0011 xxxx patterns respectively. figure 18 illustrates how interrupts are enabled and faults cleared. clint0 and clint1 have the same format as mask0 and mask1 respectively, but the action is to clear the interrupt latch and status register 0 bit corresponding to the lower nibble of the command. interrupt handling figure 18. interrupt handling table 8. null commands spi data bits 76543210 write 000xxx00 reset null commands are described in detail in the status registers section of this document. table 9. mask0 register spi data bits 76543210 write 0010xxxx reset 1111 table 10. mask1 register spi data bits 76543210 write 0011xxxx reset 1111 to status register various faults from clint command from maskx:n register fault net 0 net n int mask bit int clear int source s r latch
analog integrated circuit device data freescale semiconductor 33 33937a functional device operation logic commands and registers mode command this command is sent by sending binary 010x xxxx data. table 11. setting interrupt masks mask:bit description mask0:0 over-temperature on any gate drive output generates an interrupt if this bit is set. mask0:1 desaturation event on any output generates an interrupt if this bit is set. mask0:2 vls under-voltage generates an interrupt if this bit is set. mask0:3 over-current error ?if the over-current comparator threshold is exceeded, an interrupt is generated. mask1:0 phase error ?if any phase comparator output is not at the expec ted value when an output is command on, an interrupt is generated. this signal is the xor of the phase comparator ou tput with the output drive state, and blacked for the duration of the desaturation blanking interval. in fullon mode, this signal is blanked and cannot generate an error. mask1:1 framing error ?if a framing error occurs, an interrupt is generated. mask1:2 write error after locking. mask1:3 reset event ?if the ic is reset or disabled, an interrupt occurs. since the ic will always start from a reset condition, this can be used to test the interrupt mechanism because when the ic comes out of reset, an interrupt will immediately occur. table 12. mode command spi data bits 76543210 write 0 1 0 0 desaturation fault mode 0 fullon mode mode lock reset 0000 ? bit 0 ? mode lock is used to enable or disable mode lock. this bit can only be cleared with a device reset. since the mode lock mode can only be set, this bit prevents any subsequent, and likely erroneous, mode, deadtime, or mask register changes from being received. if an attempt is made to write to a register when mode lock is enabled, a write error fault is generated. ? bit 1 ? fullon mode. if this bit is set, programmed deadtime control is disabled, making it is possible to have both high and low side drivers in a phase on simultaneously. this coul d be useful in special applications such as alternator regulators, or switched-reluctance motor drive applications. there is no deadtime control in fullon mode. input signals directly control the output stages, synchronized with the internal clock. this bit is a ?0?, after reset. until over written, the ic operates nor mally; deadtime control and logic prevents both outputs from being turned on simultaneously. ? bit 3 ? desaturation fault mode controls what happen when a desaturation event is detected. when set to ?0?, any desaturation on any channel causes all six output drivers to shutoff. the drivers can only be re-enabled by executing the clint command. when 1, desaturation faults are completely ignored. bit 3 controls behavior if a desaturation, or phase error event is detected. the possibilities are: ? 0: default: when a desaturation, or phase error event is detected on any channel, all channels turn off and generates an interrupt, if interrupts are enabled. ? 1: disable: desaturation /phase error channel shutdown is disabled, but interrupts are still possible if unmasked. sending a mode command and setting the mode lock simultaneously are allowed. this sets the requested mode and locks out any fur ther changes.
analog integrated circuit device data 34 freescale semiconductor 33937a functional device operation logic commands and registers deadtime command deadtime prevents the turn-on of both transistors in the same phase until the deadtime has expired. the deadtime timer starts when a fet is commanded off (see figure 6 and figure 13 ). the deadtime control is disabled by enabling the fullon mode. the deadtime is set by sending the deadtime command (100x xxx1), and then sending a calibration pulse of cs . this pulse must be 16 times longer than the required deadtime (see figure 19 ). deadtime is measured in cycle times of the internal time base, f tb . this measurement is divided by 16 and stored in an internal register to provide the reference for timing the deadtime between high and low gate transactions in the same phase. for example: the internal time base is running at 20 mhz and a 1.5 s deadtime is required. first a deadtime command is sent (using the spi), then a cs is sent. the cs pulse is 16*1.5 = 24 s wide. the ic measures this pulse as 24000 ns/50 ns = 480 clock cycles and stores 480/16 = 30 in the deadtime register. until the next deadtime calibration is performed, 30 clock cycles will separate the turn off and turn on gate signals in the same phase. the worst case error immediately after calibration will be +0/-1 time base cycle, for this example +0 ns/-50 ns. note that if the internal time base drifts, the effect on dead time will scale directly. sending a zero deadtime command (100x xxx0) sets the deadtime timer to 0. however, simultaneous turn-on of high side and low side fets in the same phase is still prevented unless the fullon command has been transmitted. there is no calibration pulse expected after receiving the zero deadtime command. after reset, deadtime is set to the maximum value of 255 time base cycles (typically 15 s). the ic ignores any spi data that is sent during the calibration pulse. if there are any transitions on si or sclk while the deadtime cs pulse is low, a framing error will be generated, however, the cs pulse will be used to calibrate the deadtime figure 19. deadtime calibration table 13. .deadtime command spi data bits 76543210 write 100xxxxzero/ calibrate reset xxxx cs sclk si so deadtime command deadtime calibration pulse deadtime calibration pulse deadtime command cs sclk si so
analog integrated circuit device data freescale semiconductor 35 33937a functional device operation logic commands and registers status registers after any spi command, the status of the ic is reported in the return value from the spi port. there are four variants of the null command used to read various status in the ic. other commands return a general status word in the status register 0. there are four status registers in the ic. status register 0 is most commonly used for general status. registers one through three are used to read or confirm internal ic settings. status register 0 (status latch bits) this register is read by sending the null0 command (000x xx00). it is also returned after any other command. this command returns the following data: table 14. status register 0 spi data bits 76543210 results register 0 read reset event write error framing error phase error over-current low vls desat detected on any channel tlim detected on any channel reset 10000000 all status bits are latched. the latches are cleared only by se nding a clint0 or clint1 command with the appropriate bits set. if the status is still present, that bit will not clear. clint0 and clint1 have the same format as mask0 and mask1 respectively. ? bit 0 ?is a flag for over-temperature on any channel. this bit is the or of the latched three internal tlim detectors.this flag can generate an interrupt if the appropriate mask bit is set. ? bit 1 ?is a flag for desaturation detection on any channel. this bit is the or of the latched three internal high side desaturation detectors and phase error logic. faults are also detected on the low side as phase errors. a phase error is generated if the output signal (at px_hs_s) does not properly reflect the drive conditions. the phase error is the triple or of phase errors from each phase. each phase error is the or of the hs and ls phase errors. an hs phase error (which will also trigger the desaturation detector) occurs when the hs fet is commanded on, and the px_hs_s is still low in the deadtime duration after it is driven on. similarly, a ls phase error occurs when the ls fet is commanded on, and the px_hs_s is still high in the deadtime duration after the fet is driven on. this flag can generate an interrupt if the appropriate mask bit is set. ? bit 2 ? is a flag for low supply voltage . this flag can generate an interrupt if the appropriate mask bit is set. ? bit 3 ?is a flag for the output of the over-current comparator . this flag can generate an interrupt if the appropriate mask bit is set. ? bit 4 ?is a flag for a phase error . if any phase comparator output is not at the expected value when just one of the individual high or low side outputs is enabled, the fault flag is set. this signal is the xor of the phase comparator output with the output driver state, and blanked for the duration of the desaturation blanking interval. this flag can generate an interrupt if the appropriate mask bit is set. ? bit 5 ?is a flag for a framing error . a framing error is a spi message not containing one or more multiples of eight bits. sclk toggling while measuring the deadtime calibration pulse is also a framing error. this would typically be a transient or permanent hardware error, perhaps due to noise on the spi lines. this flag can generate an interrupt if the appropriate mask bit is set. ? bit 6 ?indicates a write error after the lock bit is set. a write error is any atte mpted write to the maskn, mode, or a deadtime command after the mode lock bit is set. a write erro r is any attempt to write any other command than the one defined in the table 7 . this would typically be a software error. this flag can generate an interrupt if the appropriate mask bit is set. ? bit 7 ?is set upon exiting rst . it can be used to test the interrupt mechanism or to flag for a condition where the ic gets reset without the host being otherwise aware. this flag can g enerate an interrupt if the appropriate mask bit is set.
analog integrated circuit device data 36 freescale semiconductor 33937a functional device operation logic commands and registers status register 1 (mode bits) this register is read by sending the null1 command (000x xx01) . this is guaranteed to not affect ic operation and returns the following data: status register 2 (mask bits) this register is read by sending the null2 command (000x xx10) . this is guaranteed to not affect ic operation and returns the following data: status register 3 (deadtime) this register is read by sending the null3 command (000x xx11) . this is guaranteed to not affect ic operation and returns the following data: table 15. status register 1 spi data bits 76543210 results register 1 read 0 desaturation mode zero deadtime set calibration overflow deadtime calibration 0 fullon mode lock bit reset 00000000 ? bit 0 ? lock bit indicates the ic registers (deadtime, maskn, clin tn, and mode) are locked. any subsequent write to these registers is ignored and will set the write error flag. ? bit 1 ? is the present status of fullon mode . if this bit is set to ?0?, the fullon mode is not allowed. a ?1? indicates the ic can operate in fullon mode (both high side and low side fets of one phase can be simultaneously turned on). ? bit 3 ?indicates deadtime calibration occurred. it will be ?0? until a successful deadtime command is executed. this includes the zero deadtime setting, as well as a calibration overflow. ? bit 4 ?is a flag for a deadtime calibration overflow . ? bit 5 ?is set if zero deadtime is commanded. ? bit 6 ?reflects the current state of the desaturation/phase error turn-off mode. table 16. status register 2 spi data bits 76543210 results register 2 read mask1:3 mask1:2 mask1:1 mask1:0 mask0:3 mask0:2 mask0:1 mask0:0 reset 11111111 table 17. status register 3 spi data bits 76543210 results register 3 read dead7 dead6 dead5 dead4 dead3 dead2 dead1 dead0 reset 00000000 these bits represent the calibration applied to the internal osci llator to generate the requested deadtime. if calibration is n ot yet performed, all these bits return 0 even though the actual dead time is the maximum.
analog integrated circuit device data freescale semiconductor 37 33937a functional device operation initialization requirements initialization requirements the 33937a provides safe, dependable gate control for 3 phase bldc motor control units when it is properly configured. however, if improperly initialized, the high side gate drive can be left in a high-impedance mode which will allow charge to accumulate from external sources, eventually turning on the high side output transistor. it is prudent to follow a well defined initialization procedure which will establish known states on the gates of all the phase drivers before any current flows in the motor. recovery from sleep mode (reset) the output gate drive is pulled low with the hold off circuit as long as vls is low, there is a power on reset condition or +5v is low. these conditions are present during a reset condition. when first coming out of a reset condition, the gate drive circuits are in a high-impedance state until the first command is given for operation. after the reset line goes high, the supplies begin to operate and the hold off circuit is deactivated. the phase input lines will not have any effect on the gate drive until both enable1 and enable2 go high and even then, the low side gate must be commanded on before the high side gate can be operated. this is to insure the bootstrap capacitor has been charged before commencing normal operation. then the high side gate must be commanded on and then off to initialize the output latches. a proper initialization sequence will place the output gate drives in a low-impedance known condition prior to releasing the device for normal operation. a valid initialization sequence would go something like this: 1. reset goes high (enable1 and enable2 remain low) 2. spi commands to configure valid interrupts, desat mode and dead time are issued 3. spi command to clear all interrupt conditions 4. enable1 and enable2 are set high (ls outputs are now enabled) 5. pa_ls, pb_ls and pc_ls are toggled high for about 1us (hs outputs are enabled, but not latched) 6. toggle npa_hs, npb_hs and npc_hs low for dead time plus at least 0.1us (hs outputs are now latched and operational). end of initialization. doing step 6 simultaneously on all hs inputs will place the motor into high side recirculation mode and will not cause motion during the time they are on. this action will force the high side gate drive out of tri- state mode and leave it with the hs_g shorted to hs_s on all phases. the hs output fets will be off and ready for normal motor control. step 5 and step 6 can be done on all the stated inputs simultaneously. it may be desirable for the hs (step 6) to be toggled simultaneously to prevent current from flowing in the motor during in itialization. note the inputs pa_ls, pb_ls, pc_ls, npa_hs, npb_hs and npc_hs are edge sensitive. toggling the ls inputs enables the hs drivers, so for the hs drivers to be initialized correctly the edge of the input signal to the hs drivers must come after the ls input toggle. a failure to do this will result in the hs gate output remaining in a high- impedance mode. this can result in an accumulation of charge, from internal and external leakage sources, on the gate of the hs output fet causing it to turn on even though the input level to the 33937a would appear to indicate it should be off. when this happens, the logic of the 33937a will allow the ls output fet to be turned on without taking any action on the hs gate because the logic is still indicating that the hs gate is off. the initial ls input transition from low to high needs to be after both enable inputs are high (the device in normal mode) for the same reason. the delay between enable and the ls input should be 280 ns minimum to insure the device is out of stby mode. once initialized the output gate drives will continue to operate in a low-impedance mode as commanded by the inputs until the next reset event.
analog integrated circuit device data 38 freescale semiconductor 33937a functional device operation initialization requirements figure 20. full initialization table 18. full initialization timing description time description min comments t pu_vdd , t pu_vls power up time from reset 2.0 ms reset must remain high long enough for vdd and vls to reach the full regulated voltage. the normal time for this to occur is specified as 2.0 ms maximum. if there is more capacitance on vls or vdd than the normal values given in the specification, this time may need to be increased. in general, the time may be safely scaled linearly with the capacitance. if the charge pump is used it may also increase this time. an estimate of increased time, due to the charge pump, would be to add 25%. for example, the nominal vls capacitance is 2.2 f on each pi n, the power up time should be increased to 4.0 ms, 5.0 ms if using the charge pump. t 1 end of spi communication to en1 and en2 rising edge 0ns t 2 en1 and en2 rising edge to first ls output command 280 ns restricted by en1 and en2 propagation delay t 3 initial ls on period 1.0 s nominally 1.0 s is more that enough. the calculated value is 5*c boot (r sense + r dson_ls ). 100 ns for default recovery. t 4 ls of to hs on 0ns no defined maximum, but hs is undefined until beginning of toggle on the hs t 5 initial hs on period 100 ns + dead time minimum: dead-time + 100 ns to guarantee the hs is switched. maximum: same limitations as normal oper ation. unlimited time if leakage currents are less than trickle charge pump margin. t 6 hs off to normal operation 0ns immediately begin normal operation int spi cs px_hs px_ls en1-2 rst vdd vls vpwr vsup t pu_vdd t pu_vls t 1 t 2 t 4 t 5 t 6 t 3
analog integrated circuit device data freescale semiconductor 39 33937a functional device operation initialization requirements recovery from standby mode or a fault when the 33937a is placed in standby mode or a fault condition causes a shutdown, the gate outputs are all driven low. the high side gate drive is then disabled and locked to prevent unauthorized transitions. this requires an initialization sequence to recover normal operation at the end of this mode of operation. the initialization sequence is nearly identical to recovery from sleep mode, with the modification that the initial pulse to the low side control inputs can be reduced to a 100 ns pulse (the low side gates may not actually change state). then the initialization is completed by cycling the high side gates to re-engage the gate drive and insure that it is in the proper state prior to resuming normal operation. a valid initialization sequence would go something like this: 1. spi command to clear all interrupt conditions 2. enable1 and enable2 are set high (ls outputs are now enabled) 3. pa_ls, pb_ls and pc_ls are toggled high for at least 100 ns (hs gate drive outputs are enabled) longer if bootstrap capacitors need charged. 4. toggle npa_hs, npb_hs and npc_hs low for dead time plus at least 100 ns. end of initialization. doing step 4 simultaneously on all hs inputs will place the motor into high side recirculation mode and will not cause motion during the time they are on. this action will restore the high side gate drive operation and leave it with the hs_g shorted to hs_s on all phases. the hs output fets will be of f and ready for normal motor control. step 3 and step 4 can be done on all the stated inputs simultaneously. in fact it is desirable for the hs (step 4) to be toggled simultaneously to prevent current from flowing in the motor during initialization. note the inputs pa_ls, pb_ls, pc_ls, npa_hs, npb_hs and npc_hs are edge sensitive. toggling the ls inputs enables the hs drivers, so for the hs drivers to be initialized correctly the edge of the input signal to the hs drivers must come after the ls input toggle. a failure to do this will result in the hs gate output remaining locked out from input control. the initial ls input transition from low to high needs to be after both enable inputs are high (the device in normal mode) for the same reason. the delay between enable and the ls input should be 280 ns minimum to insure the device is out of stby mode. figure 21. recovery initialization the horizontal divisions are not to scale, they are a reference to show the sequence of operation. either individual npx_hs and px_ls or npx_combined may be used. npx_combined is defined as both npx_hs and px_ls tied together or operated to the same logic level simultaneously. int spi ncs px_combined npx_hs px_ls en2 en1 clear 0.1 s 0.1 s
analog integrated circuit device data 40 freescale semiconductor 33937a functional device operation initialization requirements ic initialization this process flow will initialize the ic and its software environment. 1. apply power (v sys ) to module 2. remove rst (rst goes high, en1 and en2 are still low) 2.1. when rst rises above the threshold, the device will power-up. the charge pump (if configured) will start, allow v dd and v ls to stabilize. 3. initialize registers 3.1. clear all interrupt status flags (send cint0 and cint1) 3.2. initialize mask register by sending 0010 xxxx or 0011 xxxx to mask out unwanted interrupts. 3.3. set desired dead time either by commanding zero dead time or calibrating the dead time. 3.4. send mode command with desired bits, and also the lo ck bit. e.g. 01000001. this prevents further mode changes. 4. bring en1 & en2 high 5. initialize the outputs 5.1. command all px_hs to logic 1 (high side off) 5.2. command all px_ls to logic 1 (commanding low side on). the input must transition from low to high after en1 and en2 have gone high. 5.3. wait for the bootstrap capacitors to charge (about 1us typically) 5.4. command all px_ls to logic 0 (command low side off) 5.5. command all px_hs to logic 0 (command high side on) 5.6. command all px_hs to logic 1 (command high side off) the device is now ready for normal operation. interrupt handler when an interrupt occurs, the general procedure is to send null0 and null1 commands to determine what happened, take corrective action (if needed), clear the fault and return. because the return value from an spi command is actually retu rned in the subsequent message, main-loop software that tries to read sr1, sr2 or sr3, may experience an interrupt between sending the spi command and the subsequent read. thus if these registers are to be read, special care must be taken in the software to ensure that the correct results are being interpr eted.
analog integrated circuit device data freescale semiconductor 41 33937a typical applications typical applications figure 22. typical application diagram using charge pump (+12 v battery system) vsup vpwr pump vpump pgnd main charge pump oscillator uv detect 5v reg. vdd control logic t-lim rst en1 en2 int px_hs px_ls 3 3 cs si sclk so phase_x 3 oc_out oc_th amp_out amp_n amp_p vls_cap px_ls_s px_ls_g px_hs_g px_hs_s px_boot vdd vls trickle charge pump hold -off circuit high -side driver low -side driver vls reg. i-sense amp. over-cur. comp. phase comp. desat. comp. to motor 3 x + - + - v sys + - vsup vsup 1.4v gnd to other two phases +12v nom. phase x output to adc r g_hs r g_ls (optional) (optional) c x_boot r sense phase return vpwr pump d1 d2 c1 c2 c6 c3 c5 c4 r1 r2 r3 r fb q hs q ls
analog integrated circuit device data 42 freescale semiconductor 33937a typical applications figure 23. high-voltage applicat ion diagram (+42 v battery system) vsup vpwr pump vpump pgnd main charge pump oscillator uv detect 5v reg. vdd control logic t-lim rst en1 en2 int px_hs px_ls 3 3 cs si sclk so phase_x 3 oc_out oc_th amp_out amp_n amp_p vls_cap px_ls_s px_ls_g px_hs_g px_hs_s px_boot vdd vls trickle charge pump hold -off circuit high -side driver low -side driver vls reg. i-sense amp. over-cur. comp. phase comp. desat. comp. to motor 3 x + - + - v sys + - vsup vsup 1.4v gnd to other two phases phase x output to adc r g_hs r g_ls (optional) (optional) c x_boot r sense phase return vpwr pump c2 c6 c3 c5 c4 r1 r2 r3 r fb q hs q ls +42v nom. +14v nom.
analog integrated circuit device data freescale semiconductor 43 33937a typical applications figure 24. power dissipation profile of application using charge pump reference application with: ? pump capacitor: 1.0 ? f mlc ? pump filter capacitor: 47 ? f low esr aluminum electrolytic ? pump diodes: mur120 ? output fet gate charge: 240 nc @ 10 v ? pwm frequency: 20 khz ? switching single phase below approximately 17 v the charge pump is actively regulating v pwr . the increased power dissipation is due to the charge pump losses. above this voltage the charge pump oscillator shuts down and v sys is passed through the pump diodes directly to v pwr . 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1 5 10152025303540 supply voltage (v) power dissipated (w)
analog integrated circuit device data 44 freescale semiconductor 33937a typical applications figure 25. power dissipation profile of application not using charge pump reference application with: ? output fet gate charge: 240 nc @ 10 v ? pwm frequency: 20 khz ? switching single phase ? no connections to pump or vpump ? vpwr connected to v sys if vpwr is supplied by a separate pre-regulator, the power dissipat ion profile will be nearly flat at the value of the pre-regu lator voltage for all v sys voltages. 0.000 0.100 0.200 0.300 0.400 0.500 0.600 0.700 0.800 0.900 1.000 1.100 1.200 1.300 1.400 1.500 10 15 20 25 30 35 40 45 50 55 60 supply voltage (v) power dissipation (w)
analog integrated circuit device data freescale semiconductor 45 33937a packaging packaging dimension packaging packaging dimension for the most current package revision, visit www.freescale.com and perform a keyword search using the ?98asa99334d? listed below. dimensions shown are prov ided for reference only.. ek suffix (pb-free) 54-pin 98asa99334d issue c
analog integrated circuit device data 46 freescale semiconductor 33937a packaging packaging dimension (continued) packaging dimension (continued) ek suffix (pb-free) 54-pin 98asa99334d issue c
analog integrated circuit device data freescale semiconductor 47 33937a revision history revision history revision date description of changes 1.0 6/2008 ? initial release 2.0 7/2008 ? updated specifications for current sens e amplifier and overcurrent comparator ? added gain/phase curves for current sense amplifier ? added typical curves for load margin on px_cboot ? added discussion about bootstrap capacitors and requirements for external bootstrap diodes ? updated application drawings ? added vsup requirement for hold-off 3.0 11/2008 ? updated freescale form and style ? added note to vls regulator outputs (vls, vls_cap) ? changed charge device model - cdm ? corrected title to no output loads on gate drive pins, no pwm, outputs initialized ? changed in order to achieve a 100% duty cycle operati on of the high side external fets, a fully integrated trickle charge pump provides the charge necessary to maintain the external fet gates at fully enhanced levels. the trickle charge pump has limited ability to supply external leakage paths while performing it?s primary function. the graph in figure 11 shows the typical margin for supplying external current loads. these li mits are based on maintaining the voltage at cboot at least 3.0 v greater than the voltage on the hs_s for that phase. if this voltage differential becomes less than 3.0 v, the corresponding high side fet will most likely not remain fully enhanced and the high side driver may malfunction due to insufficient bias voltage between cboot and hs_s. and associated paragraphs 4.0 12/2008 ? added pcz33937aek/r2 part number throughout. ? added note and changed parameters for desaturation detector and phase comparator to dynamic electrical ch aracteristics table. ? replaced typical application diagrams (pages 40 and 41). ? page 10 remove v dd threshold (v dd falling) change note 23 5.0 4/2009 ? note 41 clarification. 6.0 9/2009 ? changed part number from pcz33937a to mcz33937a on page 1. added device variation table on page 2. 7.0 3/2011 ? revised per specific customer requirements (not published) 8.0 8/2012 ? removed part number mcz33937aek and r eplaced with part number MC33937APEK. ? removed part number mcz33937ek/r2 and specific di fferences. noted in ordering information to see specification mc33937 rev 6.0 for obsolete parts.
document number: mc33937 rev. 8.0 8/2012 information in this document is provided solely to enable system and software implementers to use freescale products. there are no express or implied copyright licenses granted hereunder to design or fa bricate any integrat ed circuits on the information in this document. freescale reserves the right to make chang es without further not ice to any products herein. freescale makes no warranty, re presentation, or guarantee regarding the suitability of its products fo r any particular purpose, nor does freescale assume any liability arising out of the application or us e of any product or circ uit, and specifically disclaims any and all liability, including wi thout limitation consequential or incidental damages. ?typical? parameters that may be provided in freescale data sheets and/or specifications can and do vary in differ ent applications, and actual performance may vary over time. all operating parameters, in cluding ?typicals,? must be validated for each customer application by customer?s te chnical experts. freescale does not convey any license under its patent rights nor the rights of others. freescale sells products pursuant to standard terms and conditions of sale, which can be found at the following address: http://www.reg.net /v2/webservices/freescale/ docs/termsandconditions.htm freescale, the freescale logo, altivec, c-5, codetest, codewarrior, coldfire, c-ware, energy efficient solutions logo, mobilegt, powerquicc, qoriq, qorivva, starcore, and symphony are trademarks of freescale semico nductor, inc., reg. u.s. pat. & tm. off. airfast, beekit, beestack, coldfire+, corenet, flexis, magniv, mxc, platform in a package, processor expert, qoriq qonv erge, quicc engine, ready play, smartmos, turbolink, vybrid, and xtrinsic are trademarks of freescale semiconductor, inc. all other product or service names are the property of their respective owners. ? 2012 freescale semiconductor, inc. how to reach us: home page: freescale.com web support: freescale.com/support

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